The present invention relates in general to the field of integrated circuit manufacturing, and more particularly, to utilizing deep trench isolation for reducing soft errors in integrated circuits.
Without limiting the scope of the invention, its background is described in connection with the manufacture of integrated circuits for use in the creation of metal oxide semiconductor (MOS) memory devices, as an example.
The growing demand for increasingly smaller and thus more cost effective semiconductor devices, e.g., with large memory capacities, has pushed the development of miniaturized structures in sub-micron technologies. The development of dynamic random access memory (DRAMs) has made possible the storage capability of several million bits of information in a single integrated circuit chip. DRAMs are memory devices in which the presence or absence of a capacitive charge represents the state of binary storage element. DRAMs, which are capable of inputting and outputting data at random, generally comprise an array of memory cells for storing data and peripheral circuits for controlling data in the memory cells. Within the array, each memory cell is electrically isolated from adjacent cells.
Typically, a MOS DRAM cell includes a single transistor and a single capacitor for storing the electrical charge corresponding to one bit of information; the cell operates by storing a charge on the capacitor for a logic 1 and storing no charge for a logic 0. With such a construction, each cell of the memory array is required to be periodically refreshed so as to maintain the logic level stored on the cell capacitor. The greater the current leakage, the more frequent the refresh cycle.
It has been found, however, that present methods for the development of large monolithic circuits have encountered numerous difficulties. One such difficulty is the problem of shrinking size in order to pack more circuitry on a chip without increasing the soft error rate. As the size of DRAM arrays, for example, is decreased, the density of the integrated circuits within the DRAM arrays is correspondingly increased. Therefore, the potential grows larger for the occurrence of soft errors caused by charges injected from the surroundings, making the device less reliable.
Such soft errors in DRAM cells have also been attributed to the vulnerability of MOS capacitors to charges generated in the substrate by ionizing radiation such as cosmic rays, noise injected from the substrate, p-n junction leakage over the entire area of the capacitor, and sub-threshold leakage of the cell transistor. A cosmic ray, for example may directly or indirectly produce an ionization path. In fact, a 5 MeV alpha particle can produce more than 200 femtocoulombs of hazardous electrons.
What is needed is a high density integrated circuit that reduces the incidence of soft errors. The present invention disclosed herein provides an integrated circuit having improved soft error protection and a method improving the soft error protection of an integrated circuit. The integrated circuit can comprise a substrate, a transistor formed in the substrate, a first region formed in the substrate having a first conductivity type, a second region below the first region having a second conductivity type, and a trench formed in the substrate having a depth at least substantially as deep as the first region. The trench is filled with a non-conductive material that forms a frame around the transistor, whereby soft errors due to electron hole pairs caused by ionizing radiation in the frame area are substantially eliminated.